Hi, I'm Buğra Tufan

ASIC/FPGA Development Engineer

Architecting high-performance digital systems for mission-critical environments. Expertise in high-speed logic, SoC integration, and robust hardware design.

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Buğra Tufan

About Me

I'm an FPGA Development Engineer with over four years of experience in digital design, specializing in RTL design and frontend synthesis flow. Currently at Mynaric in Munich, Germany, I work on laser communication terminals for space applications.

My journey spans from designing ASICs at Yongatek to optimizing high-speed DDR interfaces at Rohde & Schwarz. I hold a Master's degree from Koç University where I researched readout ICs for superconducting nanowire single-photon detectors.

I'm passionate about building tools that make hardware development more efficient—like my open-source project Axion-HDL, which automates AXI register space generation from simple annotations.

4+
Years Experience
3
Companies
20+
GitHub Repos

Experience

My professional journey in digital design

Aug 2024 – Present

FPGA Developer

Mynaric, Munich, Germany

Developing FPGA designs for laser communication terminals. Working with Xilinx gigabit transceivers, SFP interfaces, and PetaLinux on Zynq UltraScale+ MPSoC.

Sep 2022 – Jun 2024

FPGA Development Engineer

Rohde & Schwarz, Munich, Germany

Designed Network-on-Chip interconnects and optimized high-speed DDR interfaces. Developed VUnit testbenches and gained experience with Xilinx Versal.

Sep 2020 – Aug 2022

Digital Design Engineer

Yongatek Microelectronics, Istanbul, Turkey

Led top-level integration of TSMC 65nm SoC. Implemented DVB-RCS2 PHY algorithms and developed H.264 encryption modules for ASIC.

Sep 2017 – Aug 2018

Embedded System Developer

Gumush Aerospace and Defense, Istanbul, Turkey

Developed embedded software for nanosatellites using STM32 and MSP430 microprocessors.

Featured Projects

Open source tools and HDL implementations

Axion-HDL

Automated AXI4-Lite register space generation from VHDL annotations, YAML, XML, or JSON. One command generates VHDL modules, C headers, and documentation. 230+ tests, GHDL verified.

Python VHDL AXI4-Lite CLI Tool
GitHub Docs
9 stars 1 fork

Radix-2 FFT VHDL

VHDL implementation of radix-2 FFT pipeline algorithm for IEEE-754 single precision floating point data format. High-performance signal processing core.

VHDL DSP IEEE-754
GitHub
⭐ 10 stars

AES Encrypt Core

VHDL implementation of 128-bit AES Encryption Core. Synthesizable, standard-compliant cryptographic IP for FPGA and ASIC.

VHDL Cryptography Security
GitHub

Make Silicon

A streamlined toolkit for initializing FPGA and ASIC project directories with standardized scripts and folder structures.

Makefile Automation DevOps
GitHub

Consulting Services

Expert guidance for your hardware and embedded projects

FPGA/ASIC Design

RTL design in VHDL/Verilog, synthesis optimization, timing closure, high-speed interfaces (PCIe, DDR, GTH/GTY), and full-chip integration for ASIC tapeouts.

  • RTL Design & Verification
  • Xilinx/Intel FPGA Development
  • ASIC Backend Flow
  • High-Speed Serial Interfaces

Embedded Development

Bare-metal and RTOS firmware development for ARM Cortex-M, MSP430, and other microcontrollers. Hardware abstraction layers, drivers, and real-time systems.

  • STM32 / ARM Cortex-M
  • FreeRTOS / Zephyr
  • Peripheral Drivers
  • Power Optimization

Embedded Linux

Linux BSP development, PetaLinux/Yocto builds, device tree configuration, kernel driver development, and system optimization for Zynq/MPSoC platforms.

  • Yocto / PetaLinux
  • Kernel & Driver Development
  • Zynq UltraScale+ MPSoC
  • Boot Optimization
Get in Touch

Get in Touch

I'm always interested in hearing about new opportunities in FPGA development, digital design, or consulting projects. Feel free to reach out!

Email bugratufan97@gmail.com
LinkedIn in/bugratufan
GitHub bugratufan